The present invention relates to a semiconductor memory device, and more particularly to a delay locked loop circuit for controlling internal operations so that data corresponding to external commands applied to the semiconductor memory device are output in synchronization with a system clock.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into memory cells selected by addresses.
As the operating speed of the system increases and semiconductor integrated circuit technologies are advanced, semiconductor memory devices are required to input and output data at higher speed. In order for faster and stable operations of semiconductor memory devices, a synchronous semiconductor memory device has been developed, which inputs/outputs data in synchronization with a system clock received from the outside. However, the synchronous semiconductor memory device is still insufficient to meet the required data input/output speed. Thus, a double data rate (DDR) synchronous semiconductor memory device has recently been developed, which inputs/outputs data at a rising edge and a falling edge of the system clock, respectively.
In order to input/output data at the rising and falling edges of the system clock, respectively, the DDR synchronous semiconductor memory device should process two data in each cycle of the system clock. Especially, timing for outputting data should be synchronized exactly with the rising and falling edges of the system clock. To this end, a data output circuit in the DDR synchronous semiconductor memory device serves to control timings for outputting the data internally and transferring the data, to output data in synchronization with the rising and falling edges of the system clock input thereto.
The system clock input to the semiconductor memory device is transferred to the data output circuit through a clock input buffer, a clock transfer line, and the like in the semiconductor memory device. The transferring of the system clock is inevitably accompanied by a delay. In such a case, the data output circuit outputs data to the outside in synchronization with the system clock, which has been delayed before being received by the data output circuit. Then, an external device receives the output data that is not synchronized with the rising and falling edges of the system clock from the semiconductor memory device. Therefore, the external device cannot recognize the correct data output time, and thus cannot sense the data normally.
To address this limitation, the semiconductor memory device is provided with a delay locked loop circuit for compensating the system clock with the delay time due to the internal circuits of the semiconductor memory device through which the system clock is transferred to the data output circuit. The delay locked loop circuit duplicates the delay time of the system clock due to the clock input buffer, clock transfer line and the like through which the system clock is transferred. The delay locked loop circuit adjusts the phase of the input system clock to compensate the system clock for the duplicated delay time, and then outputs the internal clock to the data output circuit. That is, the system clock input to the semiconductor memory device is compensated for the delay time to lock its phase before being transferred to the data output circuit. The data output circuit outputs data in synchronization with the delay locked clock, and the external device determines that the data are output in exact synchronization with the system clock.
Actually, the delay locked clock is transferred from the delay locked loop circuit to the output buffer one cycle before the data output time so that the data are output in synchronization with the transferred delay locked clock. This is intended for allowing the data to be seen as if they are output in exact synchronization with the rising and falling edges of the system clock input to the semiconductor memory device in the outside of the semiconductor memory device. That is, the data output is advanced by a time greater than the delay time of the system clock due to the internal circuits of the semiconductor memory device. As such, in the outside of the semiconductor memory device, the data is seen as if they are output in exact synchronization with the rising and falling edges of the system clock. Accordingly, the delay locked loop circuit is a circuit for finding how soon the data should be output to compensate the data output timing for the delay time in the semiconductor memory device.
Recently, as the semiconductor memory device is required for a rapid operation, the frequency of the system clock input to the semiconductor memory device is increased, and the number of data processed in each cycle of the system clock is also increased from two to four. The newly developed high speed semiconductor memory device utilizes an additional data clock having a frequency two times higher than the system clock together with the system clock, as a reference for the data input/output. For example, if the system clock, which serves as a reference for inputting/outputting commands and addresses, has a frequency of 1 GHz, the data clock has a frequency of 2 GHz. In order that the semiconductor memory device operates in synchronization with the high frequency clock, the delay locked loop circuit, which controls the timing for outputting data to the outside by compensating the system clock for the delay time, can finely and accurately control the variation of the delay time adjusted for the phase lock even if the frequency of the clock is increased.
The conventional delay locked loop circuit detects a phase difference between the system clock and the internal clock reflecting the delay time. Then, the conventional delay locked loop circuit adjusts the phase of the system clock through a delay line including unit cells having a delay time corresponding to the detected phase difference, and feeds back the result. The conventional delay locked loop circuit repeats the operation of tracking the phase difference until the phase is locked. The operation of the conventional delay locked loop circuit includes: compensating the system clock for the delay time, which is obtained by the modeling of the delay time caused during the input/output of the system clock; detecting the phase difference between the compensated clock and the reference clock; controlling the delay elements to reduce the phase difference. The operations of the delay locked loop circuit utilizing the negative delay effect may be accompanied by unwanted change in the delay time or a distortion of the clock due to the variations in the environments such as voltage level, temperature, pressure and process. In addition, the conventional delay locked loop circuit has following limitations: such a phase locked operation takes a somewhat long time; a duty cycle ratio may be changed and be exposed to a variety of noises, a jitter, and the like while varying the phase of the clock using a duplicate delay unit for compensating the clock for the delay time caused by the clock input/output path and the delay line for applying the delay time to the clock through a plurality of delay cells.
As described above, as the semiconductor memory device receives a high frequency clock signal to operate at high speed, the phase locked operation takes a long time, the duty cycle ratio may be varied undesirably, and the semiconductor memory device is vulnerable to noise and jitter. Therefore, there is a demand for a new delay locked loop circuit that can overcome these limitations.